1. Field of the Invention
The present invention relates to a self-aligned silicide (Salicide) process. More particularly, the present invention relates to a self-aligned silicide process for forming embedded dynamic random access memory (DRAM).
2. Description of the Related Art
In a conventional embedded memory, memory transistors and logic circuit transistors are formed on the same piece of wafer. The advantages of integrating memory and logic transistors together include an increase yield, a shorter cycle time and a lower manufacturing cost. However, due to the different needs of memory transistors and logic transistors, processing steps must be adjusted accordingly. For example, response from logic devices must be as quick as possible. On the other hand, the inter-refreshing time of memory capacitors must be as long as possible. Therefore, the memory transistors must be fabricated in a manner slightly different from the logic devices.
FIG. 1 is a schematic cross-sectional view showing a portion of a conventional embedded DRAM with both logic devices and memory cell transistors therein.
As shown in FIG. 1, a substrate 100 that includes a logic device region 102 and a memory cell region 104 is provided. Two transistors 108 and 110 and a capacitor 112 together in the memory cell region 104 constitute a DRAM cell. A transistor 106 is formed in the logic device region 102.
To increase the speed of operation of the transistor 106 in the logic device region 102, self-aligned silicide layers 114 are formed over the transistor terminal regions. However, in order to extend the inter-refreshing period of memory cell, resistance at the junction between the capacitor 112 and the source/drain region 116 of the transistor 110 must be increased. Consequently, a silicide layer is usually not formed over the source/drain regions of the transistors 108 and 110 in the memory cell region 104.
In general, before self-aligned silicide layers are formed over the terminal regions of the transistor 106, a blocking layer is formed over the transistors 108 and 110. The blocking layer is removed after the self-aligned silicide process is complete.
Since no silicide layer covers the source/drain regions 116 of the transistors 108 and 110, resistance at source/drain junctions is high. However, due to the absence of a silicide layer, resistance at the word line or gate junctions of the transistors 108 and 110 will also be high. Hence, operating speed of the memory cell will drop.
Ideally, silicide layers are formed over the gate terminals and the source/drain terminals of transistors in the logic device region as well as the gate word lines of transistors in the memory cell region. No silicide layer is formed over the source/drain regions of the transistors in the memory cell region. However, such a configuration can hardly be achieved through a conventional process.